The present invention is directed generally to the field of integrated circuits and, more particularly, to the field of integrated circuit testing and diagnostics.
Defects of various types occur during the manufacturing process of an integrated circuit (IC). Failure analysis (FA) is used to characterize defects that occur during fabrication of an integrated circuit (IC) so that the manufacturing process and/or design can be corrected to improve yield or test escape. However, with the increasing complexity of the IC manufacturing process, the task of FA is becoming ever more difficult. FA has been identified as one of the Grand Challenges in the near term. Software-based fault diagnosis involves using a CAD tool to identify the potential locations and types of defects in an IC by analyzing its tester response to applied stimuli at the logic level. Fault diagnosis has typically augmented the complex task of physical analysis of failure (PFA) by acting as a first step towards locating defects. However, with PFA becoming increasingly complex and time-consuming, diagnosis must take on a more important role in FA. Most defects exhibit logic-level misbehavior and, therefore, can be modeled as a logical fault.
Past approaches to fault diagnosis include techniques for fault localization and those that attempt to identify a particular type of fault, e.g., bridging faults, opens, delay faults, etc. It has been argued that localization alone is not sufficient and that using accurate fault models for diagnosis improves accuracy. The latter approach of using specific fault models for fault diagnosis works well when a defect's behavior can be conjectured fairly accurately. However, it has been shown that the commonly used fault models may be insufficient to model the complex behaviors of defects in nanoscale technologies. One approach is to use several fault models and response matching algorithms for fault diagnosis. However, those approaches require vital information regarding the logical behavior of defects for correct diagnosis.
To summarize, the primary question addressed by all the diagnosis methods described above is: “Is it there?”, where “it” refers to an assumed defect behavior. A diagnosis is deemed successful if the answer to the above question is “yes.” However, an important question often overlooked is: “What else can be there?” For example, a diagnosis approach that focuses on two-line shorts returns success if the behavior of a two-line short is identified from an IC's tester response. Other questions that should be asked at this stage, but are typically not addressed, include: “Is the defect really only a two-line short?” “Is the defect an N-line short, where N>2?” “Is it a multiple stuck-at fault that affected N sites, or is it an open with a behavior that mimics a short?”